A flip-flop is an electronic circuit that has two stable states and thus is capable of serving as one bit of memory. (The term “flip-flop” is used, in the context of the present patent application and in the claims, to denote both clocked flip-flops and transparent flip-flops, commonly known as latches.) Violation of the prescribed operating conditions of a flip-flop can cause metastability, in which the logical state of the flip-flop oscillates unpredictably before settling in a random stable state. For example, metastability may occur if the data input of a clocked flip-flop changes during the prescribed setup time period before the triggering clock transition and/or the prescribed hold time period following a given clock transition.
Generally, digital logic circuits are designed to avoid metastable conditions. In some applications, however, a circuit may be designed intentionally for metastability. For example, U.S. Pat. No. 7,302,458, whose disclosure is incorporated herein by reference, describes a random number generator using metastable elements that are synchronized by a set of flip-flops. The output of the stabilizing flip-flops is compared and used to generate counter events.